1. Field of the Invention
This invention relates generally to optimization of digital integrated circuits, and more particularly, to small gate-length biasing of transistors to improve performance characteristics.
2. Description of the Related Art
Modern-day digital integrated circuits are complex devices that often must meet high performance standards. Due to their complexity, the design and simulation of integrated circuits is also a complex task. Furthermore, the modern-day manufacture of integrated circuits has now reached minimum feature sizes that are down into the nanometer scale. Each new technology generation brings ever-tighter requirements for manufacturing process control. As a result, there is a demand for approaches that can improve the performance characteristics of integrated circuits, preferably with minimal disruption to existing design and manufacturing process.
For example, power consumption is one aspect of circuit performance. High power dissipation in integrated circuits shortens battery life, reduces circuit performance and reliability, and has a large impact on packaging costs. Power in complementary metal oxide semiconductor (CMOS) circuits consists of a dynamic component and a static component, which is primarily due to leakage currents. While lowered supply voltages (and consequently lowered threshold-voltages) and aggressive clock gating can achieve dynamic power reduction, these techniques typically increase leakage power and therefore cause its share of total power to increase. Manufacturers face the additional challenge of leakage variability: recent data indicates that leakage of microprocessor chips from a single 180 nm wafer can vary by as much as 20×. Thus, leakage power has become an important design concern for the system-level chip designer since it is becoming an ever-increasing component of total dissipated power, with its contribution projected to increase from 18% at 130 nm to 54% at the 65 nm node.
Leakage current is generally composed of three major components: (1) subthreshold leakage, (2) gate leakage, and (3) reverse-biased drain-substrate and source-substrate junction band-to-band tunneling leakage. The reverse-biased diode junction leakage does not depend on gate-length (also called channel length), gate leakage is linearly proportional to gate-length, and subthreshold leakage has an exponential dependence on gate-length. Subthreshold leakage, which is also proportional to operating temperature, is usually the dominant contributor to total leakage at 130 nm and is likely to remain so in the future. This is especially true since gate leakage, which has only a small dependence on temperature, is often much reduced compared to subthreshold leakage in technologies using thick gate insulator thicknesses or high dielectric constant insulators, which is likely the case for technology nodes less than 65 nm.
Another leakage source is gate induced drain leakage (GIDL), which is primarily due to minority carriers in drain depletion region. GIDL is important primarily for moderately doped drains, since lightly doped drain (LDD) regions do not have high enough electric fields to trigger GIDL. LDD regions should not narrow due to channel length increases. Additionally, GIDL is a strong function of channel width and oxide thickness but not channel length. GIDL largely depends on the gate-drain overlap region, which does not change with changes in channel length.
Proposed techniques for leakage power reduction generally include the use of multiple supply (Vdd and Vss) and gate threshold (Vth) voltages, and the assignment of input values to inactive gates such that leakage is minimized. Such leakage reduction methodologies can be divided into two classes depending on whether they reduce standby leakage or runtime leakage. Standby techniques reduce leakage of devices that are known not to be in operation, while runtime techniques reduce leakage of active devices.
Several techniques have been proposed for standby leakage reduction. Body biasing or VTMOS-based approaches dynamically adjust the device Vth by biasing the body terminal. This technique has also been used to reduce leakage of active devices. Multi-threshold CMOS (MTCMOS) techniques use high-Vth CMOS (or NMOS or PMOS) devices to disconnect one or both of Vdd or Vss from logic circuits implemented using low Vth devices in standby mode. In source biasing, a positive bias is applied in standby state to source terminals of off devices. Other techniques include the use of transistor stacks and the use of input-vector control. Among the drawbacks of these techniques are increased logic design complexity, circuit layout area overhead, and the coarse-grained nature of the resulting power reductions.
Currently, to the inventors' knowledge, the primary mainstream approach to runtime leakage reduction is the multi-Vth manufacturing process. One drawback to this technique is the rise in process costs due to additional steps and masks. However, the increased costs have been outweighed by the resulting leakage reductions and multi-Vth processes are common. One complication facing the multi-Vth approach is the increased variability of Vth for low-Vth devices. This occurs in part due to random doping fluctuations, as well as worsened drain induced barrier lowering (DIBL) and short-channel effects (SCE) in devices with lower channel doping. The larger variability in Vth degrades the achievable leakage reductions of multi-Vth approaches and worsens with continued MOS scaling. Moreover, multi-Vth methodologies do not offer a smooth tradeoff between performance and leakage power. Devices with different Vth typically have a large separation in terms of performance and leakage, for instance a 15% speed penalty with a 10× reduction in leakage for high-Vth devices.
Gate-length (LGate) also affects device leakage currents. Large changes to gate-lengths, however, even in devices within non-critical gates, result in heavy delay and dynamic power penalties. Large changes would also necessitate large changes in design methodology, for example, potentially significant changes in design rules. In addition, cell layouts with large changes to gate-lengths are not layout-swappable with their nominal versions, resulting in substantial engineering change order (ECO) overheads during layout. Moreover, traditional sizers, which focus on width-sizing or multi-Vth processes for optimization, perform poorly with gate-length sizing because it is fundamentally different than width sizing.
Thus, there is a need to improve digital circuits, for example, by reducing leakage current and thus leakage power, while minimally impacting delay performance and/or design and manufacturing processes.